When both transistors are OFF the resistor pulls the output to ground. Only when both transistors are ON is there a direct “connection” from the output to Vcc and it’s ON.
When both inputs energize the output will become high. The resistor is a high value pulldown, and will drop the output voltage across it when active. This is an AND gate; does not invert
First of all, collect for yourself quality technical books and in this case, logic gates that you will use for reference. Don’t rely on WIKIPEDIA, Google or similar. They are only a cruch and can lead you down the wrong path. It’s not important to know all the answers but, where to find the right answers.
I think I understand where OP is coming from. Because of R-Out, any base current flowing from input B will raise the potential at the output well above 0v, even if input A is off.
On the other hand, in a NAND gate configuration with a pull-up resistor and the output taken from the collector of transistor A, you pretty much get VCC or zero volts at your output. Much nicer to work with.
I remember now why this is wrong. I screenshot it a few months ago and forgot my thought process when I posted it. If input B is on and input A is off the output is still on. This is an OR condition, not an AND condition.
Wikipedia is right and you’re wrong: that IS an AND.
0 & 0: 0
0 & 1: 0
1 & 0: 0
1 & 1: 1
When both transistors are OFF the resistor pulls the output to ground. Only when both transistors are ON is there a direct “connection” from the output to Vcc and it’s ON.
The only way I can think you’ve come to that conclusion is if you’re not aware that A and B are the inputs, and Out is the result.
Wikipedia is never wrong! The fact, not theory.
Been years and years since I’ve had to know this stuff but it looks like an AND gate to me.
Click AND bait AND switch
When both inputs energize the output will become high. The resistor is a high value pulldown, and will drop the output voltage across it when active. This is an AND gate; does not invert
[removed]
First of all, collect for yourself quality technical books and in this case, logic gates that you will use for reference.
Don’t rely on WIKIPEDIA, Google or similar. They are only a cruch and can lead you down the wrong path.
It’s not important to know all the answers but, where to find the right answers.
Wikipedia is wrong soooo many times but this time it had it right, by accident I guess but it’s right
It’s a poor implementation, but it is an AND gate.
I think I understand where OP is coming from. Because of R-Out, any base current flowing from input B will raise the potential at the output well above 0v, even if input A is off.
On the other hand, in a NAND gate configuration with a pull-up resistor and the output taken from the collector of transistor A, you pretty much get VCC or zero volts at your output. Much nicer to work with.
That said, this is still an AND gate.
I remember now why this is wrong. I screenshot it a few months ago and forgot my thought process when I posted it. If input B is on and input A is off the output is still on. This is an OR condition, not an AND condition.