This is a new iteration of a cartridge for my 6502-based game console, the GameTank.
The previous version had 2MB of NOR Flash, and mapped that into a 32KB address space by using a shift register to set the higher address bits.
This design adds 32KB of SRAM that is powered by a coin cell battery when the system is powered down. The previously-unused eighth output bit of the shift register is now used to select between the Flash and the SRAM.
As with the previous design, any accesses to the upper half of the cartridge address space will go to the top of the Flash memory. The lower half of the cartridge space is a sliding window controlled by the shift register. This ensures that the CPU can read the Reset Vector on a cold boot.
The battery-backup scheme is to just use a couple of diodes to separate the two power sources. A small amount of current leaks out when the system is off, which is enough to partially preserve some system RAM but otherwise seems harmless.
This is a new iteration of a cartridge for my 6502-based game console, the GameTank.
The previous version had 2MB of NOR Flash, and mapped that into a 32KB address space by using a shift register to set the higher address bits.
This design adds 32KB of SRAM that is powered by a coin cell battery when the system is powered down. The previously-unused eighth output bit of the shift register is now used to select between the Flash and the SRAM.
As with the previous design, any accesses to the upper half of the cartridge address space will go to the top of the Flash memory. The lower half of the cartridge space is a sliding window controlled by the shift register. This ensures that the CPU can read the Reset Vector on a cold boot.
The battery-backup scheme is to just use a couple of diodes to separate the two power sources. A small amount of current leaks out when the system is off, which is enough to partially preserve some system RAM but otherwise seems harmless.
[Schematic here](http://forum.6502.org/download/file.php?id=16933&mode=view)
Looks awesome!