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The Microchip Era Is Giving Way to the Megachip Age — It’s getting harder to shrink chip features any further. Instead, companies are starting to modularize functional blocks into “chiplets” and stacking them to form “building-” or “city-like” structures to continue the progression of Moore’s Law. 6
The Microchip Era Is Giving Way to the Megachip Age — It’s getting harder to shrink chip features any further. Instead, companies are starting to modularize functional blocks into “chiplets” and stacking them to form “building-” or “city-like” structures to continue the progression of Moore’s Law.
View Reddit by cad908 – View Source
Just realized this is behind the paywall. Here is a free link: https://www.wsj.com/articles/chiplet-amd-intel-apple-asml-micron-ansys-arm-ucle-11659135707?st=ya2xhaip8nkcfnf&reflink=desktopwebshare_permalink
I don’t get the connections. So on a chip there are 7 layers of copper traces. Now I can see that we put transistors and wires on both sides. The top and bottom wires/traces are wide enough to be aligned to traces on the next chip. They land on each other. So you stack everything, fill it with CO to reduce the copper, press.
The pictures show stacks so high they become cubes. So you grind the sides and polish them and then apply copper like on the other sides.
So memory is cool. So the inside of the cube is memory or special circuitry which is only fired up occasionally. Or low clock rate low leakage
Laying out PCBs is getting harder as they put chips with higher pn counts into smaller packages with tighter pin pitches. 0.5mm pitch BGAs are a joke.
Isn’t this just miniaturizing the PCB?
Is this just the current alternative for now until we find a reliable and cheap way to manufacture chips with CNTFETS?
System On a Chip is a sensible way to incorporate other people’s IP and shrink the BOM costs.