No products in the cart.
I implemented risc-v in logisim. Here it is running a Fibonacci program written in C 9
I implemented risc-v in logisim. Here it is running a Fibonacci program written in C
I implemented risc-v in logisim. Here it is running a Fibonacci program written in C from electronics
View Reddit by mort96 – View Source
As the title says, I implemented risc-v (specifically, the baseline RV32I ISA) in Logisim. It’s not quite done yet, but you can already write real C programs, compile them for RV32I, and load them into my CPU’s ROM.
Here’s the git repo: https://github.com/mortie/rv32i-logisim-cpu/ — To play with it yourself, open rv32_logisim_cpu.circ in [Logisim-evolution](https://github.com/logisim-evolution/logisim-evolution).
Screenshots:
* [The main CPU control logic](https://raw.githubusercontent.com/mortie/rv32i-logisim-cpu/main/screenshots/cpu.png)
* [The ALU](https://raw.githubusercontent.com/mortie/rv32i-logisim-cpu/main/screenshots/alu.png)
What’s left:
* Currently, only loading and storing 32-bit words at a time is possible. RV32I specifies ways to load/store 16-bit half-words as well as individual bytes, but I just ignore that at the moment in my memory controller.
* It’s not currently possible to load data from ROM. The memory controller has to be extended to map, say, the lowest megabyte of the address space to ROM.
* I need to add some kind of I/O, so that we don’t have to dig into the register file to see any output from the program.
Oh i have seen this ;).
well done mort, time to port it over now muahaha.
from the thumbnail i thought Logisim Evo added a Dark mode lol.
anyways that’s looking pretty dope! it’s always a great feeling to have something work!
i’m still struggling with my own RISC-V Implementation… mainly because i want it to use an 8-bit Data bus instead of a 32-bit one, so you can much easier fit it into a small package FPGA, use cheaper 8-bit wide Memory, and avoid unaligned access issues when programming.
i’m using a fork of Logisim Evo, called “Logisim Evo HC”. i mostly just use it because i don’t like regular Evo’s redesigns for things like registers and RAM Components, i find them ugly and unnecessarily large.
Can you export that to something like an FPGA? Be cool to see it running as hardware.
And now you’re gonna build it with 7400 series TTL? 😲
I often curse the living hell out of LogiSim even with simple stuff, let alone a CPU architecture. And then there’s this guy.
The title is one of the most nerdy sentence i hear for long time and I love it xD
We also made a RV32I on logisim a month ago as college project✌️
https://github.com/siddharth23-8/32-bit-RISC-V-Cpu-Core
Hi mort, nice to see you around still <3
(gg34)